Commit Graph

3488 Commits

Author SHA1 Message Date
chengruichang 9f3da1cbae [Frontend][Paddle] Fix pool2d op (#11029)
* fix pool2d op

* [frontend][Paddle] Fix pool2d Op

* reformat files
2022-04-18 13:49:41 +09:00
Valery Chernov fafabc96c1 [VirtualMachine] Zero copy in set_input when input is DLTensor (#11003)
* method of creating of NDArray from external DLTensor was implemented

* set input without copying for DLTensor source

* code clean up

* update description and comments after review

Co-authored-by: Valery Chernov <valery.chernov@deelvin.com>
2022-04-15 15:31:01 -07:00
Hua Jiang 351f31b51c [Runtime][PipelineExecutor]Add forwarding queue logic for set input. (#10990)
* [Runtime][PipelineExecutor]Add forwarding queue logic for set input.
When the set_input function get called, a runtime of pipeline may not
yet finish the former computation work then the new set_input call would
break the current computation logic, to avoid such issue, we add the
forwarding queue logic to guarantee the order of input data consuming.

* polish the documents.
2022-04-16 07:03:04 +09:00
billishyahao 37db213a84 [QNNParam] Refactor the implmentation of QNNParam (#11011)
* The patch is to simplify the implmentation of QNNParam and make it more friendly to Python 2.x.

* Empty-Commit

* fix error about boolean value of Tensor with more than one value is ambiguous.
2022-04-15 10:13:19 -07:00
Eric Lunderberg 8bfe3bbb3c [Arith] Updated arith::DetectIterMap to keep extent=1 components (#10980)
* [Arith] Updated arith::DetectIterMap to keep extent=1 components

Previously, arith::DetectIterMap simplified the output expression by
replacing iteration variables with extent==1 with their value.  This
prevented the return value from being used in
arith::InverseAffineIterMap to solve for the variable, as it no longer
existed in the returned expressions.

This commit changes arith::DetectIterMap to keep the iteration
variable even if extent==1, and adds a motivating unit test that
requires this updated behavior.

* Updated to retain default behavior of DetectIterMap

To avoid breaking existing test cases, updated to maintain the same
default behavior, but a flag to maintain trivial iterators in the
result.

* Updated FFI and Python API for DetectIterMap
2022-04-15 10:02:56 -07:00
Masahiro Masuda a9d86e61b6 [Metaschedule] Support tuning on rocm and vulkan target (#11017) 2022-04-15 15:11:41 +09:00
JiaKui Hu 29774bddd8 [RELAY][FRONTEND] Initial OneFlow frontend support. (#8790)
* add relay.f.frontend.fm_oneflow support cnns

* support cuda

* fix mobilenetv2 and reviews

* fix: model without meta info

* support eager and yolo, add test

* fix: license

* add: tutorials

* fix: support new graph

* fix some comments

* refine

* fix concat op convert bug

* refine

* refine

* change cuda to cpu

* fix bug

* fix ci error in tvm

* fix pylint check

* delete useless file

* add skimage package in docker

* fix ci error

* fix bug

* add oneflow fronted test in ci

* merge conflict

* fix tutorial

* try to find error in ci

* revert

* merge conflict

* black oneflow

* Delete from_oneflow.py

Co-authored-by: Xiaoyu Zhang <35585791+BBuf@users.noreply.github.com>
Co-authored-by: BBuf <1182563586@qq.com>
2022-04-15 14:14:35 +09:00
Masahiro Masuda a34731b7fc [ROCM] DP4A intrinsic support for TE/TIR (#11009)
* [ROCM] Support dp4a on AMDGPU by sdot4 intrinsic

commit 0225f2bfe3f413cd4764c2dba6c922af2520146b
Author: Masahiro Masuda <masahi129@gmail.com>
Date:   Thu Apr 14 08:56:10 2022 +0900

    share op strategy between cuda and rocm

commit 762c7e8611c9ec3cca3321428e2362c81fe89b9b
Author: Masahiro Masuda <masahi129@gmail.com>
Date:   Thu Apr 14 08:28:34 2022 +0900

    fixed rocm batch_matmul strategy for mixed i8i8i32

commit ce53e8d141f7f901303ec6a91674337cbf2b2384
Author: Masahiro Masuda <masahi129@gmail.com>
Date:   Thu Apr 14 06:17:30 2022 +0900

    add rocm sdot4 TIR intrin

commit f4562b991f9180b61be7339b2890de1584656c10
Author: Masahiro Masuda <masahi129@gmail.com>
Date:   Thu Apr 14 06:03:44 2022 +0900

    rocm sdot4 works

commit 6cc62805f82dd884a18a1c4c0e9bae5866e00da0
Author: Masahiro Masuda <masahi129@gmail.com>
Date:   Thu Apr 14 05:32:07 2022 +0900

    more wip

commit 0602f4a3157d4cb5a3f280a3a3c514bb6535aac8
Author: Masahiro Masuda <masahi129@gmail.com>
Date:   Thu Apr 14 03:47:37 2022 +0900

    Squashed commit of the following:

    commit 65b8bcf955f44540d6a52c8416e60f3047c8366c
    Author: Masahiro Masuda <masahi129@gmail.com>
    Date:   Wed Apr 13 20:36:49 2022 +0900

        [WIP] adding DP4A support to rocm

    commit 4f8f308ab6bb85ef3bdcc2b8e846c2eea15f2167
    Author: Masahiro Masuda <masahi129@gmail.com>
    Date:   Wed Apr 13 14:03:25 2022 +0900

        Squashed commit of the following:

        commit 1711be38a17e3b6171350009f1da05824cd0b340
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Wed Apr 13 13:11:40 2022 +0900

            fixed condition for real

        commit 8a48fb5262e80e318cd81d5ff51bf95fd5eb576e
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Wed Apr 13 09:57:42 2022 +0900

            Revert "Skip applying sch_rule when both ann and sch_rule are defined"

            This reverts commit 4915c6a5a91ff87038e71f8aff9f31db684b4a95.

        commit daea033d2cb06388ef27ddadb80fc5bce72181d2
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Mon Apr 11 09:31:05 2022 +0900

            [Metaschedule] Support rocm and spirv

        commit eb0cae2c779808cced074d189e8f487bf46ea89f
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Wed Apr 13 07:25:04 2022 +0900

            dp4a works

        commit 4915c6a5a91ff87038e71f8aff9f31db684b4a95
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Wed Apr 13 06:13:45 2022 +0900

            Skip applying sch_rule when both ann and sch_rule are defined

        commit 7b3d71c6b21a9c5de9ef2b89d0a7db2800a5f3a2
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Wed Apr 13 04:40:31 2022 +0900

            fixed intrin description

        commit 7666cd7a5b0ce182791662673fbe45944c84d0ae
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Tue Apr 12 19:59:47 2022 +0900

            add DP4A intrin

        commit 7086bdb75546a2680d12dc8f80c040cea23f729a
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Tue Apr 12 19:03:44 2022 +0900

            works

        commit db343974bfae86e51078e40e6170022a782d8e0a
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Tue Apr 12 12:49:52 2022 +0900

            more hack to tensorize loop mapping to make resnet50 e2e work

        commit 2409674a7884a60beb50d7aa3345c4b907b8cd13
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Mon Apr 11 13:40:59 2022 +0900

            wip support pad + qnn.conv2d folding

        commit 613cb7ec33b6df41f1ebe0f0a0ac8eca7c73cff1
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Sun Apr 10 12:04:08 2022 +0900

            hack to tensorize loop mapping to make conv2d work

        commit 9e4f9df6a409396a8a4a20d967c4f51accf5d210
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Sun Apr 10 11:34:13 2022 +0900

            wrap tensorize with try/catch

        commit d4b496d858da0ae43063d47cb03a28b803d0269f
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Sun Apr 10 11:33:39 2022 +0900

            revert change in task_scheduler.cc

        commit 476129be7b286f5d109402280aea585e89f6dc1d
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Sat Apr 9 05:54:10 2022 +0900

            try / catch in ThreadedApply

        commit d8226ff26f25eba17d4000f25131822874bdc2cc
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Fri Apr 8 17:17:59 2022 +0900

            filter out invalid candidate

        commit 2632899a2759885d338e25f2a25ba0b2c555f0c3
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Fri Apr 8 10:09:48 2022 +0900

            try graceful exit in parallel_for_dynamic

        commit 9d6741c3dd29c4dde861aa1d3b2ca85f560f5ac6
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Fri Apr 8 09:35:51 2022 +0900

            [QNN] Fix broadcast for invalid axis

        commit 6ccde0959343ce4246ef99505b4f54de469a1a5c
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 20:51:15 2022 +0900

            refactor rewrite_tensorize

        commit 2ce206699f10b03b9611c4683018f7e0c70c7eb5
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 20:48:17 2022 +0900

            allow missing schedule_rule in post order apply

        commit 3a69353a29abfc454e28d4e530d22a3e2043712e
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 19:42:48 2022 +0900

            refactor rewrite_tensorize

        commit 43e0b2f7f98299679807aaf1ffb13cce2b5f5ce3
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 18:25:14 2022 +0900

            rewrite_vnni -> rewrite_tensorize

        commit 823797e2627a9bfa812b72019468569ee79eb4c6
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 18:12:12 2022 +0900

            VNNI -> WithIntrin

        commit 4284a47e5933aa89c1c3362b15ad53b14782fc81
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 17:45:41 2022 +0900

            introduce TileForIntrin

        commit b87ef32e30e1e71b3f39789f7289976a8cba4ab4
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 17:34:04 2022 +0900

            move TilingwithTensorIntrin to auto_tensorize.cc

        commit 2fc118b3726586ba13f7de950beaa299b83a0af3
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 17:28:45 2022 +0900

            clean up headers

        commit d8b2aa325c91b524bec22dc1ec2fc52c9f060fce
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 17:09:32 2022 +0900

            clean up using namespace

        commit eb05d25e2b71f4a1232a8796d1413011ec7629d3
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 17:03:05 2022 +0900

            refactored init

        commit 5e6b0a08d447c0470c2c8a993e4bd62673e34fe3
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 16:57:14 2022 +0900

            compiled

        commit 2b8c430e2fec7ceb285eed7bc7aa73bb9a74a997
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 12:51:55 2022 +0900

            wip MultiLevelTiling refactor

        commit 7c21a9fea0511c88bd82f49f799b5198252df40a
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:58:33 2022 +0900

            function doc string not supported by tvmscript

        commit 40f9742bc9c3aa11e8c2c0551d1827ad47fc0f39
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:56:45 2022 +0900

            update vnni intrin name

        commit 4814f825a5315efd2a3da8c36d2ce6b5df5447cd
        Merge: e0c5eb84b 07bbb38f7
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:44:47 2022 +0900

            Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni

        commit 07bbb38f7fb52db4a2ecde3d5c87cf4d5cd000a1
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:24:56 2022 +0900

            more lint fix

        commit 15e60b42362cc64b1428b219c8eada414d1b8372
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:16:08 2022 +0900

            black

        commit 7a757fe53758e06418ea1367b348b47c8cd2dcf9
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:12:54 2022 +0900

            pylint

        commit 9a3e508b6f4529158e703b4617f2ddaa351a89eb
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 10:58:52 2022 +0900

            simplify import

        commit d8e43ecf1c0a79a2c195ff31e1e699a447a11335
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 10:52:50 2022 +0900

            use vectorlow/high in arm intrin

        commit 625cd2774ec455307646b0c26bb3971d89613d1e
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 10:34:57 2022 +0900

            fixed offset factor

        commit 69e72b6b612588e670937e003435afa647030ceb
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 10:12:02 2022 +0900

            Add ARM intrin

        commit 1351fdea6b22f231a290a6c28e06732c9cf993cf
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 08:27:27 2022 +0900

            use buffer syntax sugar

        commit 0ced85fd097ed48aad8714912718d8735791e1fb
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 08:17:43 2022 +0900

            rename vnni.py to x86.py

        commit 38a5aca87ec438446593a3af17760339211f5ad9
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 07:24:44 2022 +0900

            add VNNI unittest

        commit 88b763ec48c20cf68db8bc3bae3fa3ae78996ee8
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 07:10:06 2022 +0900

            refactored existing test using VNNI intrin

        commit 711a0076d9be2b9aa80ada67e1edda5ba1fdf1fd
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 07:04:58 2022 +0900

            [TIR] Add VNNI dot product intrinsic for TIR

        commit e0c5eb84bf6a0ad2ba0cddc4bdf22a799dc4b8a0
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:42:26 2022 +0900

            merge fix

        commit b171748139e53f0cf75ff4b6fde436f9d8a5fe91
        Merge: 71fe3bdf0 82e152a3c
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:33:59 2022 +0900

            Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni

        commit 71fe3bdf02ae10ddbe090a4fd1020f545a05bb41
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 06:57:38 2022 +0900

            move tensor intrin under tir

        commit 0c51badef45af2a1025ab42fe38d1b3f07ab493e
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 06:12:39 2022 +0900

            remove log

        commit fed910e03eb94c169d4a160b8f3cad406d04c6aa
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 06:11:22 2022 +0900

            more revert

        commit 7150aff9fba167d88dbfb40d48727de8a144b9c0
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 06:10:44 2022 +0900

            revert stmt_functor change

        commit 155107b98b09c5e5cc7f19afbd327b0557a02843
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 06:10:09 2022 +0900

            refactored RewriteVNNI a bit

        commit ca15255e3a882b89b05bb83079640c929fb63096
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 05:41:13 2022 +0900

            add RewriteVNNI

        commit dc9f71d5e3122b50fa8ae6a4462f959f13870b05
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 05:38:56 2022 +0900

            vectorized init loop

        commit fcc31ee20ddfafd47f566bf98ff40a9f684d12eb
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 04:55:36 2022 +0900

            tensorize worked

        commit 2b534377a45b9ab84bf35c3d7c03ecae7616d17f
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Wed Apr 6 19:11:05 2022 +0900

            TilingwithTensorIntrin works

        commit 86baa31e773fc864f77dc113bc9a93b79f3fc652
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Wed Apr 6 08:58:27 2022 +0900

            Ported auto-tensorization code

        commit 82e152a3c91144041ade783116a50565ebb48b89
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:24:56 2022 +0900

            more lint fix

        commit 88d9bdd3b21302bc2dd068a990df15c375a1a8ef
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:16:08 2022 +0900

            black

        commit 31fe7eb8075445161d804d170772eac8e90d3425
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 11:12:54 2022 +0900

            pylint

        commit 7876754effc40ad089349534dacd75df19d38fc4
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 10:58:52 2022 +0900

            simplify import

        commit 56f2e9a85069426021e2872eb1da95bf134ac7e0
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 10:52:50 2022 +0900

            use vectorlow/high in arm intrin

        commit 995cc8d6fcec70a3fadcfb1c6fee7b9f0b5a0951
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 10:34:57 2022 +0900

            fixed offset factor

        commit 86bbd4955b34257d68d957cb4a2536aea3ef9bac
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 10:12:02 2022 +0900

            Add ARM intrin

        commit 120fd96e80307b4301ee3fc93e6793e0b40485f0
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 08:27:27 2022 +0900

            use buffer syntax sugar

        commit 0f0682d00c3961afd1f492ae55f180c5b5502767
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 08:17:43 2022 +0900

            rename vnni.py to x86.py

        commit f88c31ead1fa6db4bfd2c88eeaf5f665e4c6dddb
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 07:24:44 2022 +0900

            add VNNI unittest

        commit 6cc80094adac398762924b0b31a4c741417ba9dc
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 07:10:06 2022 +0900

            refactored existing test using VNNI intrin

        commit 11a29c704cdaad96aeeca39c9c753ef006d27a50
        Author: Masahiro Masuda <masahi129@gmail.com>
        Date:   Thu Apr 7 07:04:58 2022 +0900

            [TIR] Add VNNI dot product intrinsic for TIR

* cleanup

* black

* update dot prod intrin

* add mattr kind

* conv2d topi test working

* add dense and bmm test

* add conv2d relay test

* add tir intrin test

* pylint
2022-04-14 10:13:13 -07:00
Michalis Papadimitriou 529da9bd56 [TensorRT][BYOC] Minor refactoring to handle constants in pattern-based ops for TRT (#10994)
Co-authored-by: Michalis Papapdimitriou <mpapapdimitriou@octoml.ai>
2022-04-14 08:34:12 -07:00
Matthew Barrett 1cf0c0a5bf [CUDNN] Add partitioning support for fused conv2d+bias+act (#10997)
cuDNN has kernel support for the pattern conv2d+bias+act,
although as of v8 only relu is supported as the activation.
2022-04-14 17:50:17 +09:00
XuZhi 52f52c83de [BYOC][ACL] Fix list is not supported as an input node (#10801)
* [BYOC][ACL] Fix list is not supported as an input node

* fix clang lint error

* fix compile warnning

* fix python module import error

* rename concatenate test file

* fix always MakeACLTensor with same eid 0

* do not offload concat default

* fix concattnate test failure

* fix test failure

* fix lint error

* fix lint

* remove global var offload_concat

* support concatenate with pattern table mechanism

* disable pylint dangerous-default-value warning

Co-authored-by: XuZhi <xuzhi.xu@alibaba-inc.com>
2022-04-14 13:12:54 +09:00
Krzysztof Parzyszek 985fc933f4 [Hexagon] Handle TCP server binding to unknown port (#10945)
The server IP address will be obtained from the RPC tracker, but multiple
servers must be distinguishable. To enable this, set a unique key when
starting a server, and use that key when starting a session.
2022-04-13 19:34:01 -07:00
Chris Sullivan e370ed4597 [Hexagon] Less aggressive adb state clean up (#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.

* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction

* Only attempt to forward ports not in use by
adb or the system.
2022-04-13 15:19:41 -07:00
Altan Haan 11b8cd3ca1 [ONNX] Add imports for BERT contrib operators (#10949)
* EmbedLayerNormalization, Attention

* fix Attention

* SkipLayerNormalization

* fix dtype bug in Gelu

Co-authored-by: An Wang <anwang2009@gmail.com>

* missing parameterize_targets

* lint

* lint

* comments

* fix small thing

* factor out layer norm computation

* layernorm func

* add optional args to test

* upgrade onnxrt version

* no upgrade onnx

* fix tests

* int32

* fix tests

Co-authored-by: An Wang <anwang2009@gmail.com>
2022-04-13 10:25:14 -07:00
Margaret Qian 814e856851 sort axes (#10985)
Co-authored-by: Margaret Qian <mqian@octoml.ai>
2022-04-13 10:24:11 -07:00
Grant Watson 5cfb4bc3d0 [TVMC] Allow output module name to be passed as a command line argument (#10962)
* Allows module-name as a command line argument to tvmc
 * Updates microNPU graph partitioner to pass module name to PartitionGraph()
 * Updates CMSIS-NN graph partitioner to pass module name to PartitionGraph()

Change-Id: I12a4a2eef2ddc7e3c4a6c0dd8fdcab009c975bac
2022-04-13 16:50:27 +09:00
An Wang 597000c74e [ONNX] Add MatMulInteger importer (#10450)
* implement matmulinteger

* rm test

* rm outdated comments

* fix lint and review

* wip

* fixes

* fix

* alter tests

* extra 4x4x4 step

* comments
2022-04-13 13:25:26 +09:00
Yuanjing Shi 856b5c649a remove exception handling of autotvm xgboost extract functions (#10948) 2022-04-12 12:45:34 -07:00
Matthew Barrett 98fc6495bb [CUDNN] Add partitioning support for conv2d and log_softmax (#10961) 2022-04-13 04:25:50 +09:00
Eric Lunderberg cd6aa7b2a4 [Hexagon] Move aot/graph_executor interactions into launcher (#10907)
* [Hexagon] Move aot/graph_executor interactions into launcher

Follow-up from https://github.com/apache/tvm/pull/10581, applying
similar changes to the AOT and graph executor interactions.  This
moves the file management and upload/download from the unit tests into
the launcher.

* Added Session.test_executor to avoid duplication in graph/aot test.

* Resolve lint errors

* Moved link flags workaround out of session, into create_aot_shared

* Separated Session.get_*_executor and Session.get_executor_from_factory

* Updated to resolve lint error
2022-04-12 08:59:22 -05:00
Margaret Qian f841b63026 [ONNX] Update onnx shape op with slice index support (#10947)
* support shape op slice indices

* lint

Co-authored-by: Margaret Qian <mqian@octoml.ai>
2022-04-11 11:20:03 -07:00
Leandro Nunes 89061fafa5 [CI] Bump black version to 22.3.0 (#10960)
* Make all required adjusts in the code to comply with the new version
* Upadte ci-lint to v0.71, based on tlcpackstaging/ci_lint:20220411-060305-45f3d4a52
2022-04-11 10:24:05 -07:00
An Wang c5bd181c3d [FQ2I] Add abs to FQ2I (#10922)
* add abs to fq2i

* lint

* special case for fq2i

* np iinfo
2022-04-08 20:17:11 -07:00
Matthew Barrett 81d72e3d63 [CUDNN] Add cuDNN as a Relay partitioning target (BYOC) (#10871)
* [CUDNN] Add cuDNN as a Relay partitioning target (BYOC)

This adds infrastructure to support offloading of Relay
patterns to cuDNN. In this initial commit, only softmax
is supported.

* Refactor common TE BYOC code into separate file

* Add test guard
2022-04-09 04:23:15 +09:00
Masahiro Masuda fc0473885f [TIR] VNNI and ARM dot product intrinsic for tensorization (#10925) 2022-04-07 18:34:38 -07:00
Yuanjing Shi 19784c8c83 [TVMScript] Fixing T.buffer with typed positional arguments other than int32 (#10892)
* workaround for T.buffer with typed positional arguments

* address comments

* fix linting
2022-04-07 16:55:14 -07:00
Krzysztof Parzyszek 46675996e5 [Hexagon] Register basic strategies and schedules for common operators (#10919)
These are just placeholders to enable building full models.
2022-04-07 16:24:06 -07:00
Junru Shao 5f1f8f3421 [MetaSchedule][Refactor] Clarify Integration Logic (#10927) 2022-04-08 06:17:41 +09:00
Michalis Papadimitriou 6b4d351e9b [TRT] Minor fixes on TRT python interface (#10917)
Co-authored-by: Michalis Papapdimitriou <mpapapdimitriou@octoml.ai>
2022-04-07 21:00:03 +09:00
driazati 6cbb0f6718 [build] Update libinfo and add lint rule (#10774)
* [build] Update libinfo and add lint rule

This updates `tvm.support.libinfo()` to be in-line with the current tvm options. It also adds a lint rule to ensure these stay matched up in the future as well as a script to print out the options in more detail. This should add in communication when debugging (i.e. tell someone to run `python -c 'import tvm; tvm.support.describe()` to learn everything you need about their envrionment)

* Fix pylint

Co-authored-by: driazati <driazati@users.noreply.github.com>
2022-04-06 10:58:50 -07:00
driazati 96f701fd66 [ci] Don't diff Python files when checking formatting (#10895) 2022-04-06 09:25:22 +01:00
An Wang bf9308a8d6 [ONNX] Add imports for Gelu, BiasGelu (#10898)
As title. Adds imports for Gelu, BiasGelu from the com.microsoft onnx op domain.
2022-04-05 20:00:24 -07:00
Masahiro Masuda 3266ab1b4a [MetaSchedule] Add utility API to ease using manual schedules (#10876)
As discussed in https://github.com/apache/tvm/pull/10856#discussion_r840324560, add a utility under `meta_schedule/testing/utils.py` to clean up the database boilerplate. Also using `DummyDatabase` instead of `JsonDatabase` for further clean up, as suggested by @junrushao1994 .
2022-04-05 15:27:00 -07:00
Sevin F. Varoglu 5ec061f976 [QNN] Add per-channel quantization to add/subtract/multiply (#10718)
* Add per-channel quantization to QNN add/subtract/multiply

* Add feedback

* Add feedback - round 2

* Fix for arm test

* Add params to the test

* Try again

* Try int

* Move lhs_axis and rhs_axis

* Add as an attribute

* Add quotes
2022-04-05 09:53:14 -07:00
Jinkun Lin 41cfd3d92d [TIR] Fix int32 vs int64 mismatch in For construct. (#10595)
* Respect dtype in Scalarize.

* Add unittest.

* Fix lint.

* Promote dtype of IntImm to match loop_var in For.

* Fix dtype mismatches.

* Lint

* Lint.

* jostle ci

* Match dtype in hybrid parser.
2022-04-05 15:08:36 +09:00
Tristan Konolige a6e620937b [RUNTIME] Api to get number of runtime threads (#10896)
* [RUNTIME] Api to get number of runtime threads

Add `tvm::runtime::threading::NumThreads` and `tvm.runtime.num_threads`
as a way to get the number of threads in use by the TVM runtime.

* check if equal to hardware threads or hardware threads/2
2022-04-05 11:24:37 +09:00
Michalis Papadimitriou 98580a2a0b [BYOC][TRT] Add DFPattern support for TRT backend (#10759)
This PR adds DFPattern support for the TRT backend without removing the existing predicate registry.

Adds and extends the following:

In tensorrt.py: Add a pattern_table for all the supported ops and consumes the pre-existing op_registry checks
Adds an additional pass as unmerge_composites.cc. This is required for the TRT backend as it expects a single primitive 
function to work with, while the MergeComposite and PartitionGraph will produce a single function for each Composite 
pattern.

Adds test_inline_composites.py which tests the newly introduced pass.
Both the pattern-based and predicate-based pass sequences produce syntactically equivalent IRModules.
This is to ensure backwards compatibility."
2022-04-05 00:42:59 +01:00
heliqi 6d8cb6072b Optimize the implmentation of scale (#10884) 2022-04-04 09:38:17 +09:00
Junru Shao 6f0017a9bf [MetaSchedule][BugFix] Fix broken integration tests (#10885) 2022-04-02 09:05:01 -05:00
Gustavo Romero f745f06f04 [TVMC] tune: Use proper caps for AutoTVM and AutoScheduler (#10864)
Use proper caps in help messages when mentioning AutoTVM and
AutoScheduler tuners.

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
2022-04-01 11:40:23 -05:00
Gustavo Romero 9a34ca81f4 Fix typo in comment about kill() (#10863)
Fix typo in comment about kill method in PopenWorker class used to kill
child processes created by the worker.

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
2022-04-01 11:39:36 -05:00
Tristan Konolige adcf199294 [PROFILING] Various fixes for profile_function (#10850)
Check that the function to be profiled is actually defined.

Check that the MetricCollector used actually can time the region
requested.

Default to using the module's entry_name instead of "main".
2022-03-31 17:13:28 -07:00
Masahiro Masuda 912993ff39 [ARM] Fix int8 NCHWc compute and alter layout (#10839)
This PR fixes a bug in TE ARM int8 compute for NCHWc conv2d, introduced in https://github.com/apache/tvm/pull/10310. The compute itself, not the schedule, is broken for the following reasons:

* We are using `n_elems = 8` in https://github.com/apache/tvm/blob/e9091d6c68d5d70c28881e5c75bfe72e385c1f4d/python/tvm/topi/arm_cpu/conv2d_alter_op.py#L350. Thus, the innermost axis of the transformed kernel has extent 8: https://github.com/apache/tvm/blob/e9091d6c68d5d70c28881e5c75bfe72e385c1f4d/python/tvm/topi/arm_cpu/conv2d_alter_op.py#L375
* In the TE compute, we iterate over the innermost axis `ic_s_inner` of the kernel at https://github.com/apache/tvm/blob/f6f252f0abc8f621a96506739f9534083d1fe213/python/tvm/topi/nn/conv2d.py#L577. `ic_s_inner` has extent `n_elems` according to https://github.com/apache/tvm/blob/f6f252f0abc8f621a96506739f9534083d1fe213/python/tvm/topi/nn/conv2d.py#L566. `n_elems` is 4 by default according to https://github.com/apache/tvm/blob/f6f252f0abc8f621a96506739f9534083d1fe213/python/tvm/topi/nn/conv2d.py#L478
* The ARM code that calls this compute does not explicitly pass `n_elems`, according to https://github.com/apache/tvm/blob/e9091d6c68d5d70c28881e5c75bfe72e385c1f4d/python/tvm/topi/arm_cpu/conv2d_int8.py#L106-L108
* Thus, even though the innermost axis of the kernel has extent 8, the TE compute only loops over `n_elems = 4` of the input channel dimension. 

Initially, I tried to keep `n_elems = 8` in alter layout and fix the intrinsic definition. But `n_elems = 8` breaks tensorization pattern matching, since now the compute is doing 4x8 innermost loop but this intrinsic is supposed to do 4x4 dot product, see https://github.com/apache/tvm/blob/7896108fc41663a1fecbb52345194a93278e9e28/python/tvm/topi/arm_cpu/tensor_intrin.py#L467-L479. Setting `num_int8_elements = 8` there does fix the tensorize pattern matching, but the result was still incorrect.

Rather than fixing the intrin implementation in https://github.com/apache/tvm/blob/7896108fc41663a1fecbb52345194a93278e9e28/python/tvm/topi/arm_cpu/tensor_intrin.py#L492 to adapt for 4x8 dot product, I settled on setting `n_elems = 4` in alter layout. It turned out this change is enough to get the correct output. Moreover, `n_elems = 8` is simply wrong for the dot product path in https://github.com/apache/tvm/blob/7896108fc41663a1fecbb52345194a93278e9e28/python/tvm/topi/arm_cpu/conv2d_int8.py#L154-L155 which computes 4x4 dot product in one instruction. 

@tkonolige I suggest doing perf benchmark again, since the numbers in https://github.com/apache/tvm/pull/10310 are invalid.

cc @mbrookhart @Mousius  @junrushao1994 @vinx13
2022-03-31 17:11:32 -07:00
Margaret Qian 8775a805d1 [TVMC] Support compiling and running with VM (#10722)
* introduce vm compile path

* support vm in tvmc

* cleanup + lint

* add profiler + simplify vm case in tvmcpackage

* address comments + parametrize tests

Co-authored-by: Margaret Qian <mqian@octoml.ai>
2022-03-31 09:30:09 -07:00
Xiyou Zhou 5629f8a69e [MetaSchedule] Add Gradient Based Task Scheduler (#10366)
Co-authored-by: Junru Shao <junrushao1994@gmail.com>
2022-03-31 22:58:07 +08:00
Ivy Zhang 5814fdd7d6 prune dnnl subgraph, and add related test case. (#10835) 2022-03-30 23:42:24 -07:00
Matthew Barrett 5cacecc0c0 [CUBLAS] Add support for nn.dense and nn.batch_matmul (#10826)
* [CUBLAS] Add support for nn.dense and nn.batch_matmul

This commit includes a fix for cublas.batch_matmul
when mixed precision is being used.

* Specify args in dense
2022-03-31 13:46:31 +09:00
Krzysztof Parzyszek 6af3f36184 [Hexagon] Pass extra parameters to link_params via Map (#10830)
There is no way to pass kwargs dictionary from C++ code, so the previous
way never worked. Use TVM's Map instead, and pass the target architecture
version to the linker to use libraries specific to the architecture.
2022-03-31 13:45:15 +09:00
Xiyou Zhou 72c761c807 [MetaSchedule] Fine-Grained Rewrite Unbound Block (#10823)
In this PR we introduced more fine-grained loop spliting and reordering for Rewrite-Unbound-Block post processor based on given cuda target's attribute (`max_threads_per_block`). After this PR the performance of non-reductional kernels could improve by ~20%. Regression tests are also added.
2022-03-30 17:02:27 -07:00
Masahiro Masuda 642fc57c5e [Metaschedule] Add demonstration of selectively tuning relay ops with TIR schedules (#10793)
This demonstrates how to selectively extract and tune tasks from a whole relay mod, and apply the tuned schedule during the final `relay.build(...)`. 

This flow is entirely different from existing tests in `test_meta_schedule_tune_relay.py` where ALL ops are extracted and auto-scheduled by MS. My test extracts only int8 `dense` op, applies a manual TIR schedule on it, and leaves int8 `batch_matmul` to be scheduled by TE. 

This also serves as an example of autotvm style manual template + tensorization. The manual TIR schedule is equivalent to TE VNNI `dense` schedule in https://github.com/apache/tvm/blob/ce335c3a74185df6cc1152e53c60695d8a418d8e/python/tvm/topi/x86/dense.py#L366-L375
2022-03-30 13:30:44 -07:00