Masahiro Masuda
a34731b7fc
[ROCM] DP4A intrinsic support for TE/TIR (#11009)
* [ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
commit 0225f2bfe3f413cd4764c2dba6c922af2520146b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
commit 762c7e8611c9ec3cca3321428e2362c81fe89b9b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
commit ce53e8d141f7f901303ec6a91674337cbf2b2384
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
commit f4562b991f9180b61be7339b2890de1584656c10
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc62805f82dd884a18a1c4c0e9bae5866e00da0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
more wip
commit 0602f4a3157d4cb5a3f280a3a3c514bb6535aac8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf955f44540d6a52c8416e60f3047c8366c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308ab6bb85ef3bdcc2b8e846c2eea15f2167
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be38a17e3b6171350009f1da05824cd0b340
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5262e80e318cd81d5ff51bf95fd5eb576e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a5a91ff87038e71f8aff9f31db684b4a95.
commit daea033d2cb06388ef27ddadb80fc5bce72181d2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2c779808cced074d189e8f487bf46ea89f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a5a91ff87038e71f8aff9f31db684b4a95
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c6b21a9c5de9ef2b89d0a7db2800a5f3a2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7a5b0ce182791662673fbe45944c84d0ae
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb75546a2680d12dc8f80c040cea23f729a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db343974bfae86e51078e40e6170022a782d8e0a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674a7884a60beb50d7aa3345c4b907b8cd13
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7ec33b6df41f1ebe0f0a0ac8eca7c73cff1
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df6a409396a8a4a20d967c4f51accf5d210
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d858da0ae43063d47cb03a28b803d0269f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129be7b286f5d109402280aea585e89f6dc1d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff26f25eba17d4000f25131822874bdc2cc
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899a2759885d338e25f2a25ba0b2c555f0c3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c3dd29c4dde861aa1d3b2ca85f560f5ac6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde0959343ce4246ef99505b4f54de469a1a5c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce206699f10b03b9611c4683018f7e0c70c7eb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353a29abfc454e28d4e530d22a3e2043712e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f7f98299679807aaf1ffb13cce2b5f5ce3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e2627a9bfa812b72019468569ee79eb4c6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47e5933aa89c1c3362b15ad53b14782fc81
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32e30e1e71b3f39789f7289976a8cba4ab4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b3726586ba13f7de950beaa299b83a0af3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa325c91b524bec22dc1ec2fc52c9f060fce
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25e2b71f4a1232a8796d1413011ec7629d3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a08d447c0470c2c8a993e4bd62673e34fe3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430e2fec7ceb285eed7bc7aa73bb9a74a997
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9fea0511c88bd82f49f799b5198252df40a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742bc9c3aa11e8c2c0551d1827ad47fc0f39
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f825a5315efd2a3da8c36d2ce6b5df5447cd
Merge: e0c5eb84b 07bbb38f7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38f7fb52db4a2ecde3d5c87cf4d5cd000a1
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b42362cc64b1428b219c8eada414d1b8372
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe53758e06418ea1367b348b47c8cd2dcf9
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508b6f4529158e703b4617f2ddaa351a89eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ecf1c0a79a2c195ff31e1e699a447a11335
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd2774ec455307646b0c26bb3971d89613d1e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6b612588e670937e003435afa647030ceb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fdea6b22f231a290a6c28e06732c9cf993cf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85fd097ed48aad8714912718d8735791e1fb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca87ec438446593a3af17760339211f5ad9
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763ec48c20cf68db8bc3bae3fa3ae78996ee8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a0076d9be2b9aa80ada67e1edda5ba1fdf1fd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb84bf6a0ad2ba0cddc4bdf22a799dc4b8a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748139e53f0cf75ff4b6fde436f9d8a5fe91
Merge: 71fe3bdf0 82e152a3c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bdf02ae10ddbe090a4fd1020f545a05bb41
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51badef45af2a1025ab42fe38d1b3f07ab493e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e03eb94c169d4a160b8f3cad406d04c6aa
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff9fba167d88dbfb40d48727de8a144b9c0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b98b09c5e5cc7f19afbd327b0557a02843
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255e3a882b89b05bb83079640c929fb63096
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d5e3122b50fa8ae6a4462f959f13870b05
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee20ddfafd47f566bf98ff40a9f684d12eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b534377a45b9ab84bf35c3d7c03ecae7616d17f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31e773fc864f77dc113bc9a93b79f3fc652
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a3c91144041ade783116a50565ebb48b89
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd3b21302bc2dd068a990df15c375a1a8ef
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb8075445161d804d170772eac8e90d3425
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754effc40ad089349534dacd75df19d38fc4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a85069426021e2872eb1da95bf134ac7e0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d6fcec70a3fadcfb1c6fee7b9f0b5a0951
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd4955b34257d68d957cb4a2536aea3ef9bac
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96e80307b4301ee3fc93e6793e0b40485f0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d00c3961afd1f492ae55f180c5b5502767
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31ead1fa6db4bfd2c88eeaf5f665e4c6dddb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc80094adac398762924b0b31a4c741417ba9dc
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c704cdaad96aeeca39c9c753ef006d27a50
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
* cleanup
* black
* update dot prod intrin
* add mattr kind
* conv2d topi test working
* add dense and bmm test
* add conv2d relay test
* add tir intrin test
* pylint
2022-04-14 10:13:13 -07:00
..
2022-04-14 10:13:13 -07:00
2021-02-04 06:51:12 -08:00
2022-01-03 15:19:33 -08:00
2021-11-01 17:16:23 +00:00