Bohan Hou
859498dc01
## Summary This PR adds the initial TIRx support needed for low-level programming of Blackwell-class GPU architectures. As part of the ongoing TIRx refactor, it introduces TVMScript support for directly scripting advanced hardware features without relying on scheduling as the primary programming interface. The change keeps existing `s_tir` script support intact while making direct scripting a first-class path for TIRx programs. ## Main Changes - Add TIRx operator dispatch and layout infrastructure. - Add TVMScript support for new low-level TIRx operations. - Add analysis, transform, and lowering support for TIRx IR nodes. - Add CUDA/Blackwell-oriented codegen and intrinsic coverage. - Add Python and C++ integration points for TIRx scripting and runtime support. ## Validation - `pre-commit run --all-files` - `ninja -C build -j32` - `CUDA_VISIBLE_DEVICES=2 pytest tests/python/tirx/ -n 16` - `1723 passed, 47 skipped, 32 warnings` - `CUDA_VISIBLE_DEVICES=2 python -m pytest -v tests/python/all-platform-minimal-test` - `37 passed, 105 skipped` - `TVM_TEST_TARGETS=llvm python -m pytest -v tests/python/tirx-analysis tests/python/tirx-base tests/python/tirx-transform -n 16` - `664 passed, 25 skipped, 9 xfailed, 1 xpassed` ## Local CI Notes Some full CI-equivalent jobs were not locally reproducible because this machine is missing parts of the Apache TVM CI environment, including `llvm-config-15/17`, Vulkan, ROCm, Maven, Sphinx, Doxygen, Emscripten, and ARM/QEMU cross-toolchain components. Metal-specific tests were skipped locally because no Metal runtime is available.
263 lines
12 KiB
Python
263 lines
12 KiB
Python
# Licensed to the Apache Software Foundation (ASF) under one
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# or more contributor license agreements. See the NOTICE file
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# distributed with this work for additional information
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# regarding copyright ownership. The ASF licenses this file
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# to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance
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# with the License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing,
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# software distributed under the License is distributed on an
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# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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# KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations
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# under the License.
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# pylint: disable=missing-docstring
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# ruff: noqa: E501, E741, F841
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import tvm.testing
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from tvm.ir import assert_structural_equal
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from tvm.s_tir import dlight as dl
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from tvm.script import ir as I
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from tvm.script import tirx as T
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from tvm.target import Target
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def test_fallback():
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@I.ir_module(s_tir=True)
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class Before:
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@T.prim_func(s_tir=True)
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def main(
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A: T.Buffer((1, 32, 1, 128), "float16"),
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C: T.Buffer((1, 1, 4096), "float16"),
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):
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B = T.sblock_alloc_buffer((1, 1, 32, 128), "float16")
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for i, j, k, l in T.grid(1, 1, 32, 128):
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with T.sblock("T_transpose"):
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vi, vj, vk, vl = T.axis.remap("SSSS", [i, j, k, l])
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B[vi, vj, vk, vl] = A[vi, vk, vj, vl]
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for i, j, k in T.grid(1, 1, 4096):
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with T.sblock("T_reshape"):
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vi, vj, vk = T.axis.remap("SSS", [i, j, k])
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C[vi, vj, vk] = B[0, 0, vk % 4096 // 128, vk % 128]
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@I.ir_module(s_tir=True)
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class After:
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@T.prim_func(s_tir=True)
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def main(
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A: T.Buffer((1, 32, 1, 128), "float16"),
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C: T.Buffer((1, 1, 4096), "float16"),
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):
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T.func_attr({"tirx.is_scheduled": True})
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for ax0_fused_0 in T.thread_binding(4, thread="blockIdx.x"):
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for ax0_fused_1 in T.thread_binding(1024, thread="threadIdx.x"):
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with T.sblock("T_reshape"):
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v0 = T.axis.spatial(4096, ax0_fused_0 * 1024 + ax0_fused_1)
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T.reads(A[0, v0 // 128, 0, v0 % 128])
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T.writes(C[0, 0, v0])
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C[0, 0, v0] = A[0, v0 // 128, 0, v0 % 128]
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target = Target("nvidia/geforce-rtx-3090-ti")
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with target:
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mod = dl.ApplyDefaultSchedule( # pylint: disable=not-callable
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dl.gpu.Fallback(),
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)(Before)
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assert_structural_equal(mod, After)
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def test_fallback_reduction():
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@I.ir_module(s_tir=True)
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class Module:
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@T.prim_func(s_tir=True)
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def main(A: T.Buffer((1, 6144), "float32"), B: T.Buffer((1,), "float32")):
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for ax0, ax1 in T.grid(1, 6144):
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with T.sblock("block"):
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v0 = T.axis.spatial(1, ax0)
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v1 = T.axis.reduce(6144, ax1)
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T.reads(A[v0, v1])
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T.writes(B[v0])
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with T.init():
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B[v0] = T.float32(0)
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B[v0] = B[v0] + T.Cast("float32", A[v0, v1])
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@I.ir_module(s_tir=True)
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class Expected:
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@T.prim_func(s_tir=True)
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def main(A: T.Buffer((1, 6144), "float32"), B: T.Buffer((1,), "float32")):
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T.func_attr({"tirx.is_scheduled": True})
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for ax0_fused_0 in T.thread_binding(T.int64(1), thread="blockIdx.x"):
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for ax0_fused_1 in T.thread_binding(T.int64(1024), thread="threadIdx.x"):
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with T.sblock("block_init"):
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v0 = T.axis.spatial(T.int64(1), T.int64(0))
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T.where(ax0_fused_0 * T.int64(1024) + ax0_fused_1 < T.int64(1))
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T.reads()
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T.writes(B[0])
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B[0] = T.float32(0)
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for ax1 in range(6144):
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with T.sblock("block_update"):
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v0 = T.axis.spatial(T.int64(1), T.int64(0))
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v1 = T.axis.reduce(6144, ax1)
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T.where(ax0_fused_0 * T.int64(1024) + ax0_fused_1 < T.int64(1))
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T.reads(B[0], A[0, v1])
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T.writes(B[0])
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B[0] = B[0] + T.Cast("float32", A[0, v1])
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with Target("apple/m1-gpu"):
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mod = dl.ApplyDefaultSchedule( # pylint: disable=not-callable
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dl.gpu.Fallback(),
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)(Module)
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assert_structural_equal(mod, Expected)
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def test_fallback_irregular_spatial():
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@T.prim_func(private=True, s_tir=True)
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def func(
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var_pages: T.handle,
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var_page_table_indptr: T.handle,
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var_page_table_values: T.handle,
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var_values: T.handle,
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seq_id: T.int32,
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):
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nhead = T.int32()
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nlayer = T.int32()
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seqlen = T.int32()
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npage = T.int32()
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page_size = T.int32()
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num_total_pages = T.int32()
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num_total_seqs_plus_1 = T.int32()
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pages = T.match_buffer(var_pages, (num_total_pages, nlayer, nhead, page_size), "float16")
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page_table_indptr = T.match_buffer(var_page_table_indptr, (num_total_seqs_plus_1,), "int32")
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page_table_values = T.match_buffer(var_page_table_values, (npage,), "int32")
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values = T.match_buffer(var_values, (nlayer, nhead, seqlen), "float16")
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for l, h, pos in T.grid(nlayer, nhead, seqlen):
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with T.sblock("block"):
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vl, vh, vp = T.axis.remap("SSS", [l, h, pos])
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values[vl, vh, vp] = pages[
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page_table_values[page_table_indptr[seq_id] + T.floordiv(vp, page_size)],
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vl,
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vh,
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T.floormod(vp, page_size),
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]
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# fmt: off
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@T.prim_func(private=True, s_tir=True)
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def expected(var_pages: T.handle, var_page_table_indptr: T.handle, var_page_table_values: T.handle, var_values: T.handle, seq_id: T.int32):
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T.func_attr({"tirx.is_scheduled": True})
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nhead = T.int32()
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nlayer = T.int32()
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seqlen = T.int32()
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npage = T.int32()
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page_size = T.int32()
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num_total_pages = T.int32()
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num_total_seqs_plus_1 = T.int32()
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pages = T.match_buffer(var_pages, (num_total_pages, nlayer, nhead, page_size), "float16")
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page_table_indptr = T.match_buffer(var_page_table_indptr, (num_total_seqs_plus_1,), "int32")
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page_table_values = T.match_buffer(var_page_table_values, (npage,), "int32")
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values = T.match_buffer(var_values, (nlayer, nhead, seqlen), "float16")
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for ax0_ax1_ax2_fused_0 in T.thread_binding((nlayer * nhead * seqlen + 1023) // 1024, thread="blockIdx.x"):
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for ax0_ax1_ax2_fused_1 in T.thread_binding(1024, thread="threadIdx.x"):
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with T.sblock("block"):
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v0 = T.axis.spatial(nlayer, (ax0_ax1_ax2_fused_0 * 1024 + ax0_ax1_ax2_fused_1) // (nhead * seqlen))
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v1 = T.axis.spatial(nhead, (ax0_ax1_ax2_fused_0 * 1024 + ax0_ax1_ax2_fused_1) % (nhead * seqlen) // seqlen)
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v2 = T.axis.spatial(seqlen, (ax0_ax1_ax2_fused_0 * 1024 + ax0_ax1_ax2_fused_1) % seqlen)
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T.where(ax0_ax1_ax2_fused_0 * 1024 + ax0_ax1_ax2_fused_1 < nlayer * nhead * seqlen)
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T.reads(pages[page_table_values[page_table_indptr[seq_id] + v2 // page_size], v0, v1, v2 % page_size], page_table_values[page_table_indptr[seq_id] + v2 // page_size], page_table_indptr[seq_id])
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T.writes(values[v0, v1, v2])
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values[v0, v1, v2] = pages[page_table_values[page_table_indptr[seq_id] + v2 // page_size], v0, v1, v2 % page_size]
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# fmt: on
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target = Target("nvidia/geforce-rtx-3090-ti")
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with target:
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mod = tvm.IRModule({"main": func})
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mod = dl.ApplyDefaultSchedule( # pylint: disable=not-callable
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dl.gpu.Fallback(),
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)(mod)
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assert_structural_equal(mod["main"], expected)
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def test_gpu_fallback_ignores_non_gpu_functions():
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@I.ir_module(s_tir=True)
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class Before:
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# This function has no "target" attribute, and is scheduled
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# using the `Target.current`.
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@T.prim_func(s_tir=True)
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def gpu_func(
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A: T.Buffer((1, 32, 1, 128), "float16"),
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C: T.Buffer((1, 1, 4096), "float16"),
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):
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B = T.sblock_alloc_buffer((1, 1, 32, 128), "float16")
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for i, j, k, l in T.grid(1, 1, 32, 128):
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with T.sblock("T_transpose"):
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vi, vj, vk, vl = T.axis.remap("SSSS", [i, j, k, l])
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B[vi, vj, vk, vl] = A[vi, vk, vj, vl]
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for i, j, k in T.grid(1, 1, 4096):
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with T.sblock("T_reshape"):
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vi, vj, vk = T.axis.remap("SSS", [i, j, k])
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C[vi, vj, vk] = B[0, 0, vk % 4096 // 128, vk % 128]
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# This function is identical, except that it is explicitly
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# annotated with the "target" attribute, and is scheduled
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# based on the annotation's target.
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@T.prim_func(s_tir=True)
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def cpu_func(
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A: T.Buffer((1, 32, 1, 128), "float16"),
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C: T.Buffer((1, 1, 4096), "float16"),
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):
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T.func_attr({"target": T.target("llvm")})
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B = T.sblock_alloc_buffer((1, 1, 32, 128), "float16")
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for i, j, k, l in T.grid(1, 1, 32, 128):
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with T.sblock("T_transpose"):
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vi, vj, vk, vl = T.axis.remap("SSSS", [i, j, k, l])
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B[vi, vj, vk, vl] = A[vi, vk, vj, vl]
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for i, j, k in T.grid(1, 1, 4096):
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with T.sblock("T_reshape"):
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vi, vj, vk = T.axis.remap("SSS", [i, j, k])
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C[vi, vj, vk] = B[0, 0, vk % 4096 // 128, vk % 128]
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@I.ir_module(s_tir=True)
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class After:
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@T.prim_func(s_tir=True)
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def gpu_func(
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A: T.Buffer((1, 32, 1, 128), "float16"),
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C: T.Buffer((1, 1, 4096), "float16"),
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):
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T.func_attr({"tirx.is_scheduled": True})
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for ax0_fused_0 in T.thread_binding(4, thread="blockIdx.x"):
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for ax0_fused_1 in T.thread_binding(1024, thread="threadIdx.x"):
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with T.sblock("T_reshape"):
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v0 = T.axis.spatial(4096, ax0_fused_0 * 1024 + ax0_fused_1)
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T.reads(A[0, v0 // 128, 0, v0 % 128])
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T.writes(C[0, 0, v0])
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C[0, 0, v0] = A[0, v0 // 128, 0, v0 % 128]
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@T.prim_func(s_tir=True)
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def cpu_func(
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A: T.Buffer((1, 32, 1, 128), "float16"),
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C: T.Buffer((1, 1, 4096), "float16"),
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):
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T.func_attr({"target": T.target("llvm")})
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B = T.sblock_alloc_buffer((1, 1, 32, 128), "float16")
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for i, j, k, l in T.grid(1, 1, 32, 128):
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with T.sblock("T_transpose"):
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vi, vj, vk, vl = T.axis.remap("SSSS", [i, j, k, l])
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B[vi, vj, vk, vl] = A[vi, vk, vj, vl]
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for i, j, k in T.grid(1, 1, 4096):
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with T.sblock("T_reshape"):
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vi, vj, vk = T.axis.remap("SSS", [i, j, k])
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C[vi, vj, vk] = B[0, 0, vk % 4096 // 128, vk % 128]
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with Target("cuda"):
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mod = dl.ApplyDefaultSchedule( # pylint: disable=not-callable
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dl.gpu.Fallback(),
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)(Before)
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assert_structural_equal(mod, After)
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if __name__ == "__main__":
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tvm.testing.main()
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