Bohan Hou
bb6f8aec55
This PR batches several post-bringup TIRx follow-ups, rebased onto current `main`. ### Changes - **op-dispatch**: per-call exec scope via `Tx.<scope>.op`; remove `ExecScopeStmt` - **namespaces**: split TIRx op namespaces; remove tile-primitive kind attrs - **codegen**: support explicit CUDA launch bounds - **gemm-async**: support contiguous-axis (K-major) operand slicing - **backend reorg**: move in-tree GPU backends out of core into `src/backend/<target>/` and `python/tvm/backend/<target>/` (codegen/runtime/op), with the corresponding `CMakeLists.txt` / `cmake/modules` and include-path updates ### Testing - Builds with `USE_CUDA=ON` / `USE_LLVM=ON` - The TIRx Python test suite (`tests/python/tirx/`) passes locally
9 lines
449 B
Python
9 lines
449 B
Python
# Licensed to the Apache Software Foundation (ASF) under one
|
|
# or more contributor license agreements. See the NOTICE file
|
|
# distributed with this work for additional information
|
|
# regarding copyright ownership. The ASF licenses this file
|
|
# to you under the Apache License, Version 2.0.
|
|
"""Compatibility redirect for CUDA allocation pool helpers."""
|
|
|
|
from tvm.backend.cuda.lang.alloc_pool import * # noqa: F403 # pylint: disable=wildcard-import
|