## Problem
`relax.build()` (exposed as `tvm.compile`) with
`relax_pipeline="default"` always
resolved to `default_build_pipeline`, regardless of the target.
`default_build_pipeline` does not include DLight scheduling — it is a
target-agnostic lowering pipeline. On CUDA, this left TIR functions
generated
from ops like `Clip`/`ReLU6` without thread bindings, causing
`VerifyMemory` to fail:
```
Memory verification failed: Variable `X` is directly accessed by host memory
(it is not contained in a thread environment or in the function arguments).
Did you forget to bind?
```
## Fix
When `relax_pipeline="default"` and the target is a GPU target
(`"gpu" in target.keys`), use `relax.get_default_pipeline(target)` which
includes target-aware DLight scheduling. Fall back to
`default_build_pipeline`
if no target-specific pipeline is registered.
CPU targets (`llvm`, `c`) continue to use `default_build_pipeline`
unchanged.
The CPU-specific pipeline adds `FuseOps`/`FuseTIR`/`FoldConstant` on
top,
which can DCE `call_pure_packed` calls whose results are unused —
correct
per pure semantics, but a separate concern from this fix.
Soowon Jeong
b9ced1a078