Tianqi Chen
e43879405b
[BUILD] Windows build pass on LLVM/CUDA/OPENCL ( #57 )
2017-02-27 14:30:46 -08:00
Tianqi Chen
f6c043eb79
[LLVM/RUNTIME] Support Parallel for on CPU ( #54 )
2017-02-25 23:20:39 -08:00
Tianqi Chen
2f462ccab5
[MODULE] Enable OpenCL and CUDA Modules ( #53 )
2017-02-25 20:08:02 -08:00
Tianqi Chen
efae4be0bd
[MODULE/REFACTOR] Introduce Module for AOT and runtime linking. ( #51 )
2017-02-24 10:32:11 -08:00
Tianqi Chen
8f240ee76d
[CODEGEN/LLVM] Initial support for codegen LLVM. ( #49 )
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* [LLVM] Initial support for codegen LLVM.
* Fix the naming issue of codegen
2017-02-22 10:47:54 -08:00
Tianqi Chen
c8ec41118d
[SCAN/Refactor] Refactor scan interface, enable fix point analysis. ( #47 )
2017-02-20 13:09:23 -08:00
Ziheng Jiang
5198c10010
[ARITH] DeduceBound ( #40 )
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* [PYTHON/API] Add compare and logic build-in op for Expr
* remove 'and', 'or'
* add deducer
* [WIP] bound_deducer.cc
* move IntervalSet and StrideSet into int_set_internal.h
* add multiple failure for VariablePathFinder, add EvalSign
* consider round in deduce, add success flag
* remove Visit_(Div)
* add comment, update HalideIR
* expose intset to python
* check the sign of every expr
* set return type as ExprSignType
* fine tune
* add min & max python api for interval set
* support for conditional expr
* refactor test
* add checker for BoundDeducer
* add python check test
* fix
* fix
* change range to interval; remove converter
* remove converter declaration
* remove int_set_internal.h
2017-02-17 10:56:48 -08:00
Tianqi Chen
d114dfc96e
[SCHEDULE] Mutate dataflow in schedule, refactor Stage ( #44 )
2017-02-16 19:08:50 -08:00
Tianqi Chen
820a85975f
[LANG] Introduce Scan, Bugfix Canonical ( #43 )
2017-02-13 16:39:07 -08:00
Tianqi Chen
b8f0ec504c
[LANG/PASS] InjectVirtualThread ( #38 )
2017-02-11 11:55:42 -08:00
Ziheng Jiang
526ff04c7e
[PYTHON/API] Add compare and logic build-in op for Expr ( #39 )
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* [PYTHON/API] Add compare and logic build-in op for Expr
* remove 'and', 'or'
2017-02-10 09:14:11 -08:00
Tianqi Chen
45597d0006
[LANG/PASS] Support Vectorize ( #37 )
2017-02-09 12:15:47 -08:00
Ziheng Jiang
6a62beb2b3
[FUSION] add 'void AutoFuseEwise(Schedule sch)' ( #36 )
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* [FUSION] add Fusion(Schedule)
* [FUSION] rename to AutoFuseEwise, detect whether the stage has been scheduled
* [FUSION] change to visitor pattern
* [FUSION] rename filename
* [FUSION] fine-tune the interface
* [FUSION] typo
* move elem_wise to schedule
* rename test function
2017-02-08 22:33:52 -08:00
Tianqi Chen
08505e3484
[ADDON] Allow piggy back nvcc compiler and code ( #35 )
2017-02-07 08:12:54 -08:00
Tianqi Chen
8837798888
[PASS] Canonical form simplify ( #34 )
2017-02-06 16:26:15 -08:00
Tianqi Chen
e42cc112bf
[PASS] UnrollLoop, isolate arithmetic module. ( #32 )
2017-02-04 22:41:28 -08:00
Tianqi Chen
d89917b670
[PASS] StorageFlatten and StorageSync, safe condition in schedul_ops, gemm example. ( #31 )
2017-02-04 15:46:25 -08:00
Tianqi Chen
a2c8a29b21
[SCHEDULE] Improve bound inference, support reduce codegen. ( #30 )
2017-02-02 08:41:19 -08:00
Tianqi Chen
d4af7ad6ab
[TEST/PYTHON] Add unittest folder, add a build pipeline. Rename Buffer.ptr to Buffer.data to be consistent with Array. ( #29 )
2017-01-31 14:40:47 -08:00
Tianqi Chen
891630ed4d
[CODEGEN/EXEC] CUDA, NVRTC pipeline complete ( #27 )
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* [CODEGEN] CUDA/OPENCL pipeline complete
* Hide TVMType by str in frontend
2017-01-30 19:09:22 -08:00
Tianqi Chen
ff06917c59
[API/Refactor] Unified PackedFunc for API and Generated Functions ( #26 )
2017-01-28 16:16:55 -08:00
Tianqi Chen
4242b9cff5
[API/JIT] Enable registerable global function, introduce StackVM intepreter ( #25 )
2017-01-24 23:47:07 -08:00
Tianqi Chen
01a7ce0cb6
[RUNTIME] Add Function, Unify TVMTypeCode and TVMArgTypeID ( #24 )
2017-01-23 21:41:04 -08:00
Tianqi Chen
4f1473f3a1
[CODEGEN] Add LoweredFunc, MakeAPI to build a C API function ( #23 )
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* [CODEGEN] Add LoweredFunc, MakeAPI and SplitHostDevice
* update halideir
2017-01-22 17:45:31 -08:00
Tianqi Chen
3c1020dffb
[CODEGEN] Add CodeGenC ( #22 )
2017-01-20 12:41:52 -08:00
Tianqi Chen
4d4e19ce0a
[TESTCASE] Add a mock test workflow of CUDA codegen ( #19 )
2017-01-18 15:13:52 -08:00
Tianqi Chen
9e1a5ec449
[RUNTIME] Enable OpenCL ( #17 )
2017-01-17 21:13:16 -08:00
Tianqi Chen
e9ff9a8989
[RUNTIME] Finish GPU runtime and python interface ( #16 )
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* [RUNTIME] Finish GPU runtime and python interface
* fix travis test
* fix build
2017-01-17 14:07:38 -08:00
Tianqi Chen
7e025234fe
[RUNTIME] Add interface header of runtime ( #15 )
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* [RUNTIME] Add interface header of runtime
* fix mac build
2017-01-16 14:53:26 -08:00
Tianqi Chen
7f82912bfb
[PASS] Basic storage flatten ( #13 )
2017-01-15 21:40:21 -08:00
Tianqi Chen
0992873af2
[LANG] Include buffer semnatics, introduce pylint ( #11 )
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* [LANG] Include buffer semnatics, introduce pylint
* Refactor inline add support for buffer indexing
* fix doc
2017-01-13 15:40:49 -08:00
Tianqi Chen
5fced923ef
[LANG] Enable json load/save and pickle ( #10 )
2017-01-12 10:07:37 -08:00
Haichen Shen
7250005d00
fix ctypes bug for mac ( #9 )
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* fix c_api bug for mac
* update travis
2017-01-11 15:12:45 -08:00
Tianqi Chen
39314014fe
[LANG] Change Schedule->Stage, Use Schedule for global schedule ( #8 )
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* [LANG] Change Schedule->Stage, Use Schedule for global schedule
* add numpy as dep
* add numpy installation, temporary disable osx
2017-01-11 11:29:10 -08:00
Tianqi Chen
78ea652d61
[PASS] Schedule Ops init working version ( #6 )
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* [PASS] Schedule Ops init working version
* bugfix in PassUp
2017-01-10 11:18:57 -08:00
tqchen
302c2e644f
Make Tensor comparator and hash to be aware of same op and index, init checkin of the ir generation
2017-01-08 22:41:30 -08:00
tqchen
eee0ebef17
Stronger type checker during conversion
2017-01-06 15:39:31 -08:00
tqchen
57a74936db
Rename dim_var to axis, update testcases
2017-01-06 15:08:36 -08:00
tqchen
c5395a1f84
Expose testcase as bound inference to python, now push toward the goal!
2017-01-05 20:23:38 -08:00
tqchen
54c18a6c05
Add map container and tests
2017-01-05 16:44:23 -08:00
ZihengJiang
0e99e8aa6a
Add tile operation
2016-12-12 03:03:56 +08:00
tqchen
0c72ca970e
Finish schedule operation
2016-12-05 11:21:32 +01:00
tqchen
357ad592ac
Fix Schedule structure, refactor compute to all rely on iter var
2016-12-02 14:03:22 -08:00
tqchen
3a48b323b4
Enable bracket syntax sugar to get tensor element
2016-12-01 23:19:49 -08:00
tqchen
5445a93697
Refactor to use iterVar
2016-12-01 22:15:40 -08:00
tqchen
605813e4f4
schedule over operation
2016-11-27 22:39:40 -08:00
tqchen
9ce7f0a353
Check in inline and test
2016-11-26 17:21:38 -08:00
tqchen
2fafa93577
Add Operation class
2016-11-25 12:12:37 -08:00
tqchen
adf4bfef9b
Enable attribute key in LetStmt
2016-11-19 19:41:52 -08:00
tqchen
d903342b99
Checkin Schedule and split construction in front-end
2016-11-02 22:02:01 -07:00